Silicon Logo

VLSI Symposium 2023 — Interesting Sessions

Mastodon Logo



Workshop 2: EUV Lithography & Path to High NA EUV Patterning Solutions

  • Development of Current EUV Tools and Future High NA Tools (ASML)
  • Novel Resists to Achieve Promised High NA EUV Resolution (Lam Research)
  • EUV and High NA EUV Mask Challenges (Dai Nippon Printing)
  • High NA EUV Exposure Tool Implications to Chip and Mask Layouts (IBM)
  • Resolution Capability and Stitching of Features Across the High NA Exposure Field (ASML)

Workshop 3: Towards Functional Backside: What’s Next After Backside Power Delivery?

  • System and Physical Design: Backside PDN for Mobile Applications (Google)
  • System and Physical Design: A New VLSI R&D Frontier: Cell-Level Interconnects to Enable Back-Side Power Delivery Networks (BSPDN) and Device Stacking (Intel)
  • Electronic Design Automation: Backside Clock Delivery: Opportunities and Challenges from System Design Perspectives (Georgia Tech)
  • Process and Integration: 3D Integration of SoC Power Delivery: Contacting the Standard Cell Power Grid from the Wafer Backside (imec)
  • Process and Integration: Evolution of Backside PDN and its Impact on Lithography (ASML)

Workshop 4: The Deployment of Materials to System Co-Optimization Methodology (MSCO) to Enable Rapid PPACt Assessment for Advanced Node Technology Development

  • Materials to Systems Co-Optimization: Accelerating Technological Innovations (Applied Materials)
  • Transition from Gate-All-Around to Stacked Transistor Architecture for Logic and SRAM (Synopsys)
  • Building a Methodology for Design- and System-Technology Co-Optimization (imec)
  • Design Technology Co-Optimization Solutions for Enhanced PPAC for CFET Device Architectures (Tokyo Electron)
  • Application Dependent Architectural Design Technology Innovation and Co-Optimization for Feature Rich Technologies (GlobalFoundries)

Workshop 5: Uniform and Rigorous Benchmarking of Machine Learning ICs and System

  • Benchmarking Novel AI Accelerators: Striving to Be Both Fair and Comprehensive (IBM)
  • Challenges in Designing and Evaluating Neural Processing Units (Samsung)

Workshop 6: 3D Image Sensor

  • Role and Function of LiDAR Sensor for Autonomous Driving: Beyond Autonomous Driving Level 3 (Hyundai)
  • Integrated LiDAR Sensors for L4 Autonomous Vehicles (Google)
  • Silicon-Based FMCW Imaging for Human-Like Vision (SiLC)

Short Courses

Short Course 1: Advanced CMOS Technologies for 1 nm & Beyond

  • Transistor Scaling, Nanosheets/CFET + Seq.-3D (Intel)
  • Advances in EUV lithography: From 0.33NA Technology towards High-NA and Beyond (ASML)
  • Process Technology (Incl. Equipment) for adv. Logic, Non-BEOL (Applied Materials)
  • Challenges and Innovations for Advanced BEOL Scaling at the 1nm Node and Beyond (IBM)
  • CMOS Scaling by Backside Power Delivery (imec)
  • Process Control Solutions for the Era of 3D Architecture Devices (Nova)
  • Semiconductor Packaging Revolution in the Era of Chiplets (Rapidus)
  • Device Technology for 2D Layered Semiconductor FETs: Challenge & Perspective (University of Tokyo)

Short Course 2: Future Directions in Highspeed Wireline/Optical IO

  • SerDes System Design and Implementation (Cisco)
  • Silicon Photonics Transceiver for High-Density Optical Interconnection (AIO Dore)
  • Beyond the Interconnect, a Survey of Challenges on the Way to Enabling Heterogenous Chiplets in Package (AMD)
  • Architecture and Circuit Design of High-Speed Wireline Receivers (Intel)
  • Design Considerations for High-Speed Transmitters in Wireline and Optical Communications (Broadcom)
  • Recent Developments and Challenges for NAND Flash Memory Interface (Kioxia)


Plenary Session 1:

  • Multi-Chiplet Heterogeneous Integration Packaging for Semiconductor System Scaling (A*STAR)
  • A Six-Word Story on the Future of VLSI:AI-driven, Software-defined, and Uncomfortably Exciting (Google)

Plenary Session 2:

  • Quantum Computing from Hype to Game Changer (Hitachi)
  • Searching for Nonlinearity: Scaling Limits in NAND Flash (Western Digital)

Evening Panels

  • Discussion 1: What is Scalable & Sustainable in the Next 25 Years?
  • Discussion 2: Can Universities Help to Revitalize the IC Design Industry? If So, How?

Technology Sessions

Technology Session 1: Highlight 1

  • E-Core Implementation in Intel 4 with PowerVia (Backside Power) Technology (Intel)
  • World’s First GAA 3nm Foundry platform Technology (SF3) with Novel Multi-Bridge-Channel-FET (MBCFET™) Process (Samsung)
  • Nanosheet-based Complementary Field-Effect Transistors (CFETs) at 48nm Gate Pitch, and Middle Dielectric Isolation to Enable CFET Inner Spacer Formation and Multi-Vt Patterning (imec)
  • Contact Cavity Shaping and Selective SiGe:B Low-Temperature Epitaxy Process Solution for Sub 10-9 Ω·cm2 Contact Resistivity in Nonplanar FET (Applied Materials & IBM)

Technology Session 2: Reliability and Characterisation

  • A Novel Bridge Transmission Line Method for Thin-Film Semiconductors: Modelling, Simulation Verification, and Experimental Demonstration (National University of Singapore)

Technology Session 3: NAND Flash

  • Novel Strategies for Highly Uniform and Reliable Cell Characteristics of 8th Generation 1Tb 3D-NAND Flash Memory (Samsung)
  • Beyond 10 μm Depth Ultra-High Speed Etch Process with 84% Lower Carbon Footprint for Memory Channel Hole of 3D NAND Flash over 400 Layers (Tokyo Electron)
  • Demonstration of Recovery Annealing on 7-Bits per Cell 3D Flash Memory at Cryogenic Operation for Bit Cost Scalability and Sustainability (Kioxia)
  • High Bit Cost Scalability and Reliable Cell Characteristics for 7th Generation 1Tb 4Bit/Cell 3D-NAND Flash (Samsung)

Technology Session 4: DTCO

  • Breakthrough Design Technology Co-Optimization Using BSPDN and Standard Cell Variants for Maximizing Block-Level PPA (Samsung)
  • PPA and Scaling Potential of Backside Power Options in N2 and A14 Nanosheet Technology (imec)
  • Towards DTCO in High Temperature GaN-On-Si Technology: Arithmetic Logic Unit at 300 °C and CAD Framework Up to 500 °C (MIT, Bangladeshi University of Engineering and Technology, University of Utah & Technology Innovation Institute)

Technology Session 5: Ferroelectric 1: FeFETs

  • Strategy for 3D Ferroelectric Transistor: Critical Surface Orientation Dependence of HfZrOx on Si (KAIST & KIST)
  • First Stacked Nanosheet FeFET Featuring Memory Window of 1.8V at Record Low Write Voltage of 2V and Endurance >1E11 Cycles (National Taiwan University)
  • Cold-FeFET as Embedded Non-Volatile Memory with Unlimited Cycling Endurance (Georgia Tech)

Technology Session 6: Logic Technology 1: Advanced Platforms and Device Structures

  • Intel PowerVia Technology: Backside Power Delivery for High Density and High-Performance Computing (Intel)
  • High Performance 5G Mobile SOC Productization with 4nm EUV Fin-FET Technology (Qualcomm)
  • Integration of a Stacked Contact MOL for Monolithic CFET (imec)
  • Front-side and Back-Side Power Delivery Network Guidelines for 2nm Node High Perf Computing and Mobile SoC Applications (POSTECH & Google)

Technology Session 7: Highlight 2

  • Highly Scalable Metal Induced Lateral Crystallization (MILC) Techniques for Vertical Si Channel in Ultra-High (>300 Layers) 3D Flash Memory (Kioxia & Western Digital)
  • QLC Programmable 3D Ferroelectric NAND Flash Memory by Memory Window Expansion Using Cell Stack Engine (SK Hynix)

Technology Session 8: Logic Technology 2: Advanced Processes

  • Building High Performance Transistors on Carbon Nanotube Channel (TSMC, NIST, Stanford University & UCSD)

Technology Session 9: PCM, ReRAM and Threshold Switch

  • The Chalcogenide-Based Memory Technology Continues: Beyond 20nm 4-Deck 256Gb Cross-Point Memory (SK Hynix)
  • 16-Layer 3D Vertical RRAM with Low Read Latency (18ns), High Nonlinearity (>5000) and Ultra-Low Leakage Current (~pA) Self-Selective Cells (Chinese Academy of Sciences & Huazhong University of Science and Technology)
  • High Density Embedded 3D Stackable Via RRAM in Advanced MCU Applications (TSMC & National Tsing Hua University)

Technology Session 13: Quantum Computing and Cryo-CMOS

  • Comprehensive 300 mm Process for Silicon Spin Qubits with Modular Integration (imec & KU Leuven)
  • Quantum Dots Array on Ultra-Thin SOI Nanowires with Ferromagnetic Cobalt Barrier Gates for Enhanced Spin Qubit Control (IBM & University of Basel)
  • How Fault-Tolerant Quantum Computing Benefits from Cryo-CMOS Technology (TSMC, UCLA, EPFL & National Cheng Kung University)

Technology Session 14: New Channel Material 2: InOx and 2D Material

  • 2D Materials in The BEOL (Intel)
  • Integration of Epitaxial Monolayer MX2 Channels on 300mm Wafers via Collective-Die-To-Wafer (CoD2W) Transfer (imec)
  • Towards Low Damage and fab-Compatible Top-Contacts in MX2 Transistors Using a Combined Synchronous Pulse Atomic Layer Etch and Wet-Chemical Etch Approach (imec)

Technology Session 15: In-Memory Computing

  • Write-Enhanced Single-Ended 11T SRAM Enabling Single Bitcell Reconfigurable Compute-in-Memory Employing Complementary FET (TSMC)

Technology Session 16: Logic Technology 3: Advanced Platforms and Processes

  • Characterizing and Reducing the Layout Dependent Effect and Gate Resistance to Enable Multiple-Vt Scaling for a 3nm CMOS Technology (TSMC)
  • Highly Reliable/Manufacturable 4nm FinFET Platform Technology (SF4X) for HPC Application with Dual-CPP/HP-HD Standard Cells (Samsung)

Technology Session 17: New Channel Material 3: IGZO

  • Lowest IOFF <3×10-21 A/μm in Capacitorless DRAM Achieved by Reactive Ion Etch of IGZO-TFT (imec)

Technology Session 18: DRAM/MRAM

  • 14nm DRAM Development and Manufacturing (Samsung)
  • A 135 GBps/Gbit 0.66 pJ/bit Stacked Embedded DRAM with Multilayer Arrays by Fine Pitch Hybrid Bonding and Mini-TSV (Xi’An UniIC Semiconductor, Wuhan Xinwin Semiconductor Manufacturing, University of Science and Technology of China & Chinese Academy of Sciences)
  • Highly Reliable and Manufacturable MRAM Embedded in 14nm FinFET Node (Samsung)
  • U-MRAM: Transistor-Less, High-Speed (10 ns), Low-Voltage (0.6 V), Field-Free Unipolar MRAM for High-Density Data Memory (Industrial Technology Research Institute & National Yang Ming Chiao Tung University)

Circuits Sessions

Circuits Session 2: Non-Volatile Memory and Low Power SRAM

  • A 1Tb 3b/Cell 3D-Flash Memory of more than 17Gb/mm² bit Density with 3.2Gbps Interface and 205MB/s Program Throughput (Kioxia & Western Digital)
  • A 14nm 128Mb Embedded MRAM Macro Achieved the Best Figure-Of-Merit with 80MHz Read Operation and 18.1Mb/ mm² Implementation at 0.64V (Samsung)
  • A 3.0 Gb/s/pin 4th Generation F-Chip with Toggle 5.0 Specification for 16Tb NAND Flash Memory Multi Chip Package (Samsung)
  • 3.7-GHz Multi-Bank High-Current Single-Port Cache SRAM with 0.5V-1.4V Wide Voltage Range Operation in 3nm FinFET for HPC Applications (TSMC)
  • A 112-Gb/s 58-mW PAM4 Transmitter in 28-nm CMOS Technology (UCLA)
  • A 256 Gbps Heterogeneously Integrated Silicon Photonic Microring-Based DWDM Receiver Suitable for In-Package Optical I/O (Intel)
  • A 0.32pJ/b 90Gbps PAM4 Optical Receiver Front-End with Automatic Gain Control in 12nm CMOS FinFET (Huawei & University of Toronto)
  • A 64-Gb/s Reference-Less PAM4 CDR with Asymmetrical Linear Phase Detector Soring 231.5-fsrms Clock Jitter and 0.21-pJ/Bit Energy Efficiency in 40-nm CMOS (Chinese Academy of Sciences & University of Macau)

Circuits Session 7: Digital Circuits

  • Arvon: A Heterogeneous SiP Integrating a 14nm FPGA and Two 22nm 1.8TFLOPS/W DSPs with 1.7Tbps/mm² AIB 2.0 Interface to Provide Versatile Workload Acceleration (Intel & University of Michigan)

Circuits Session 9: Advanced SRAM

  • A 3nm 256Mb SRAM in FinFET Technology with New Array Banking Architecture and Write-Assist Circuitry Scheme for High-Density and Low-VMIN Applications (TSMC)
  • A 1.9GHz 0.57V Vmin 576Kb Embedded Product-Ready L2 Cache in 5nm FinFET Technology (IBM)
  • A 4.0GHz UHS Pseudo Two-Port SRAM with BL Charge Time Reduction and Flying Word-Line for HPC Applications in 4nm FinFET Technology (Samsung)
  • A 4.24GHz 128X256 SRAM Operating Double Pump Read Write Same Cycle in 5nm Technology (TSMC)
  • A 3-nm 27.6-Mbit/mm² Self-Timed SRAM Enabling 0.48 - 1.2 V Wide Operating Range with Far-End Pre-Charge and Weak-Bit Tracking (TSMC)

Circuits Session 12: Digital Building Blocks

  • ECC-Less Multi-Level SRAM Physically Unclonable Function and 127% PUF-to-Memory Capacity Ratio with No Bitcell Modification in 28nm (National University of Singapore)

Circuits Session 20: Circuit Designs for Optical Systems

  • A 2048-Channel, 125μW/ch DAC Controlling a 9,216-Element Optical Phased Array Coherent Solid-State LiDAR (Analog Photonics)

Circuits Session 21: PIM/CIM Systems

  • A General-Purpose Compute-in-Memory Processor Combining CPU and Deep Learning with Elevated CPU Efficiency and Enhanced Data Locality (Northwestern University)
  • A Low-Voltage Area-Efficient TSV I/O for HBM with Data Rate Up to 15Gb/s Featuring Overlapped Multiplexing Driver, ISI Compensators and QEC (Samsung)
  • A 0.190-pJ/bit 25.2-Gb/s/Wire Inverter-Based AC-Coupled Transceiver for Short-Reach Die-to-Die Interfaces in 5-nm CMOS (Nvidia)
  • A Sub-500fJ/bit 3D Direct Bond Silicon Photonic Transceiver in 12nm FinFET (Optelligent, Nhanced Semiconductors, Texas A&M University & UC Davis)

Technology Focus Sessions

Technology Focus Session 1: Future Memory Directions

  • Ongoing Evolution of DRAM Scaling via Third Dimension - Vertically Stacked DRAM (Samsung)
  • Non-Destructive-Read 1T1C Ferroelectric Capacitive Memory Cell with BEOL 3D Monolithically Integrated IGZO Access Transistor for 4F² High-Density Integration (Soitec & National University of Singapore)
  • Foundry Monolithic 3D BEOL Transistor + Memory Stack: Iso-Performance and Iso-Footprint BEOL Carbon Nanotube FET+RRAM vs. FEOL Silicon FET+RRAM (Skywater, Analog Devices, Stanford University & Harvard University)

Technology Focus Session 2: BEOL/BSPDN

  • Novel Cell Architectures with Back-side Transistor Contacts for Scaling and Performance (Intel)
  • Nano-Through Silicon Vias (nTSV) for Backside Power Delivery Networks (BSPDN) (imec)
  • Applied Materials: BEOL Interconnect Innovation: Materials, Process and Systems Co-optimization for 3nm Node and Beyond (Applied Materials)
  • Block-level Evaluation and Optimization of Backside PDN for High-Performance Computing at the A14 Node (imec & ARM)
  • Structural Reliability and Performance Analysis of Backside PDN (Samsung)

Technology / Circuits Joint Focus Sessions

Technology / Circuits Joint Focus Session 1: New Computing

  • Exploring Power Savings of Gate-All-Around Cryogenic Technology (Synopsys)
  • Circuit Designs for Practical-Scale Fault-Tolerant Quantum Computing (NTT, JST RESTO, Keio University, University of Tokyo, Nagoya University & Kyushu University)

Technology / Circuits Joint Focus Session 4: 3D System Integration

  • AMD Instinct™ MI250X Accelerator Enabled by Elevated Fanout Bridge Advanced Packaging Architecture (AMD)
  • An Integrated System Scaling Solution for Future High Performance Computing (TSMC)
  • 4-Layer Wafer on Wafer Stacking Demonstration with Face to Face/Face to Back Stacked Flexibility Using Hybrid Bond/TSV-Middle for Various 3D Integration (PSMC & National Taiwan University)
  • Bumpless Build Cube (BBCube) 3D: Heterogeneous 3D Integration Using WoW and CoW to Provide TB/s Bandwidth with Lowest Bit Access Energy (Hitachi & Tokyo Institute of Technology)
  • 1Mbit 1T1C 3D DRAM with Monolithically Stacked One Planar FET and Two Vertical FET Heterogeneous Oxide Semiconductor layers over Si CMOS (Semiconductor Energy Laboratory & University of Tokyo)

Technology / Circuits Joint Focus Session 5: Automotive and Aerospace

  • Japan Aerospace Exploration Agency: How Harsh is Space? — Equations That Connect Space and Ground VLSI